1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and in particular to a contact process of metal lines for connecting a local bit line for transmitting signals in an MAT to a new bit line for transmitting signals between the MATs in a layout structure having a bit line switch between the MATs, wherein an distance between the metal lines follows 0.1 μm design rule.
2. Description of the Background Art
FIGS. 1a and 1b are plane views schematically illustrating a conventional semiconductor device of 256 k MAT structure for example.
Referring to FIG. 1a, sense amps 13 are positioned at the right and left sides of MATs 11, and sub word line drivers (SWD) 15 are positioned at the top and bottom of the MATs 11.
Here, a bit line (not shown) serves as a local bit line used only for signal transmission. The SWD is one of the elements constituting a DRAM core circuit.
Since a word line is gates of cell transistors, it has a high capacitance. In addition, the word line uses a relatively high resistance material such as polysilicon and polycide, resulting in considerable signals delays.
In order to solve the foregoing problems, a method has been suggested wherein the word line is divided into a long distance word line for transmitting signals between the MATs and a sub word line of a cell array.
The SWD usually refers to a sub word line driver array (SWD array) including a row decoder and a word line driver which are required to drive the sub word line.
For reference, a main word line is composed of a low resistance metal line, and the sub word line is composed of polysilicon or polycide.
FIG. 1b is a plane view schematically illustrating an MAT structure using hierarchical bit lines of FIG. 1a, of 128 k MAT structure.
The MAT refers to a matrix, a unit cell matrix or a sub cell array. Generally a memory cell is arranged in a matrix of 2M columns and 2N rows.
As shown in FIG. 1b, bit line switches 27 are positioned between MATs 21, sense amps 23 are positioned at both ends of the array of the MATs 21, and SWDs 25 are positioned at the top and bottom of the MATs 21.
FIG. 2 is a layout view illustrating a hierarchical bit line structure of FIG. 1b. 
As shown in FIG. 2, since the same number of metal lines as bit lines are routed, the pitch of the metal lines is reduced to half of the conventional bit lines.
Therefore, a line/space is 0.10 μm/0.10 μm under 0.10 μm design rule.
In order to prevent short between the bit line and the adjacent metal lines, a size of a contact of the metal lines/bit lines should not exceed a predetermined value. In addition, a size of a contact pattern is determined according to the amount of overlapping between the contact and the bit line and top CD widening in an etching process.
Here, when the amount of overlapping is less than 0.05 μm and an aspect ratio is about 10, a top CD of the contact is laterally widened by 0.025 μm than the size of the pattern during the etching process using a photosensitive film pattern, and thus the size of the contact pattern vertical to the metal line should not exceed 0.10 μm.
In this case, since step difference of the contact is about 2 μm, the aspect ratio is about 20, resulting in etching and plug filling difficulties. Moreover, the top CD is much more widened and short between the bit line and the adjacent metal lines occurs.
FIGS. 3a to 3c are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device, especially a cell region 100 and a peripheral circuit region 200.
Referring to FIG. 3a, an element isolating film (not shown) defining an active region is formed on a semiconductor substrate (not shown). A word line (not shown) is formed in the active region, and a bit lines 31 is formed over the word line.
Although not shown in the drawings, a bit line metal barrier layer (not shown) is formed under the bit line 31, and the bit line 21 has a hard mask layer (not shown) is formed thereon, and an insulating film spacer is formed on the sidewalls thereof.
The formation process of capacitors in the cell region 100 is as follows.
Thereafter, an interlayer insulating film 33 is formed on the entire surface. The interlayer insulating film 33 is planarized according to a planarization etching process to expose a top portion of the bit line 31.
A landing plug 35 for storage electrode is formed by etching the interlayer insulating film 33 between the bit lines 31 according to a landing plug formation process.
An etch barrier film 37 and an insulating film 39 for storage electrode is sequentially on the entire surface of the resulting structure, and then etched them according to a photoetching process using a storage electrode mask (not shown) to form a trench type storage electrode region exposing the landing plug 35.
Thereafter, a conductive layer for storage electrode having a predetermined thickness is formed on the entire surface of the resulting structure, and then etched to form a concave type storage electrode 41 in the trench type storage electrode region.
Next, a dielectric film 43 having a predetermined thickness is formed on the entire surface of the resulting structure. Here, the dielectric film 43 is composed of an insulating material having a high dielectric constant.
A plate electrode 45 is formed on the dielectric film 43, thereby forming capacitors.
An interlayer insulating film 49 planarizing the entire surface is formed on the resulting structure.
The formation process of metal line in the peripheral circuit region 200 is as follows.
An interlayer insulating film 47 planarizing the entire surface of the peripheral circuit region 200 bit line 31 is formed to have the same height as the plate electrode 45. The interlayer insulating film 49 is formed on the interlayer insulating film 47 at the same time as the cell region 100.
Referring to FIG. 3b, a contact hole 51 exposing the bit line 31 of the peripheral circuit region 200 is formed by etching the interlayer insulating films 49 and 47 according to a photoetching process using a metal line mask (not shown).
A metal barrier layer 53 is formed on the surface of the contact hole 51.
A metal line contact plug 55, preferably a tungsten layer, is formed to fill the contact hole 51.
Referring to FIG. 3c, a metal line 57 is formed to contact the bit line 31 through the contact plug 55.
Here, the metal line 57 is composed of aluminum alloy or copper.
As described above, the conventional method for manufacturing the semiconductor device has disadvantages in that the aspect ratio reaches 10 in the contact etching process and a thickness of the photosensitive film cannot be increased over a predetermined value, for example 0.86 μm under 0.19 μm design rule due to difficulties in the patterning process, and thus the top CD widening of the contact hole occurs due to a small thickness margin of the photosensitive film. As a result, it is difficult to manufacture the device in a predetermined size, which deteriorates a property of the device.